1. Field of the Invention
This invention relates to integrated circuit (IC) chips and, more particularly, to multi-chip modules for high-frequency operation.
2. Discussion of the Related Art
In the IC industry it is common to mount IC chips on a lead frame 10 of the type shown in FIG. 1. More specifically, a chip 12 is mounted on a paddle 13, and wirebonds 15 connect terminals on the chip to particular ones of the conductive fingers 11.
In the electronic memory industry, in order to increase the density of a memory module some manufacturers, as shown in FIG. 2, have interleaved N substantially identical memory chips 20.N (N=1, 2, 3 . . . ) with spacers 22 to form a vertical stack 30, which is then mounted on the paddle 13 of a lead frame 10. Wirebonds 40.N are connected between terminals on the chips and conductive fingers 50.N on the lead frame. (For simplicity only a portion of each conductive finger is depicted, and only a few of the many connections between the chips and the fingers is shown.)
Our analysis indicates that the prior art stacked memory module design is acceptable only at relatively low frequencies of operation where the transistors within the chips are the limiting factor as to access times, not the inductance external to the chips. At higher frequencies of operation, corresponding, for example, to clock frequencies above about 500 MHz, an undesirable effect known as skew results; that is, when a multiplicity of memory cells is simultaneously addressed by signals that propagate over the wirebonds, longer wirebonds such as 40.N connected to the chip at the top of the stack produce longer access times than shorter wirebonds such as 40.1, 40.2 or 40.3. More specifically, the longer wirebonds have higher self-inductance, which in turn produces higher reactive impedance than that of shorter wirebonds. At high frequencies the wirebond impedance becomes significant relative to the impedance of the CMOS logic circuitry that is typically located at the input of the memory chips, whereas at lower frequencies the wirebond impedance is so small that any skew that does result is inconsequential.
An example will be instructive. In one prior art design of the type shown in FIG. 2, nine 4 Mb memory chips are stacked to produce a module having a density of 36 Mb. Let us assume that the wirebonds have a typical elongated, circular cylindrical shape, are 1 mil in diameter, and are made of Au, which means they would have a self-inductance of 0.14 nH/mil of length in free space. Since the longest wirebond is about 1.4 mm (55 mils) long, it would have a self-inductance of 772 pH, whereas the shortest wirebond being about 0.64 mm (25 mils) long would have a self-inductance of only 350 pH. The corresponding inductive reactance at 1 GHz of the longest wirebond would be about 4.8 Ω and of the shortest wirebond would be about 2.2 Ω. (Thus, the longer wirebond has a reactance that is about 100% larger than that of the shorter wirebond.) The transmission delay through these diverging lengths of wirebond is likewise longer in the longer wirebonds than in the shorter ones. For example, we can estimate the skew as follows. We first assume the speed of signal propagation to be c=3×108 M/s. [There is no need to adjust the propagation speed for the various parameters of the wirebond (e.g., physical properties, dielectric strength) since we also assume they are common to all wirebonds.] Then, the difference in propagation delay between the longest and shortest wires (i.e., the skew) is given by (Llongest−Lshortest)/c, where L is the length of the wirebond in meters. Using the lengths of 1.4 mm and 0.64 mm above, we estimate the skew to be about 2.5 ps, which is significant at 1 GHz. In contrast, at much lower frequencies the reactance of the wirebonds is not sufficiently large to cause significant skew.